Conventional (100)-oriented silicon or silicon-on-insulator (SOI) substrates are commonly used in the field of microelectronics. In comparison with other known surface orientations of silicon substrates, the (100)-orientation provides the highest mobility for electrons. However, the (100)-orientation is not advantageous for the hole mobility. In fact, within the group of surface orientations of commercially available for silicon wafers it provides the poorest mobility. This is detrimental for the performance of pMOS (metal-oxide-p-semiconductor) devices on (100)-silicon.
It has been established that silicon substrates with a (110)-orientation provide the best mobility for holes. However, this orientation is detrimental for the electron mobility, i.e. for nMOS (metal-oxide-n-semiconductor) devices, cf. M. Yang et al., IEEE TED, Vol. 53, No. 5, May 2006, pp. 965-978.
As is well known, CMOS (complementary metal-oxide-semiconductor) devices incorporate both types, nMOS and pMOS devices, on a single substrate (chip). To achieve optimum mobility for majority charge carriers in both device types on a single chip, proposals have been made to provide dual-orientation substrates with first lateral surface regions having a (100)-orientation for nMOS devices, and with second lateral surface regions having a (110)-orientation for pMOS devices.
US 2006/0276011 A1 describes methods for fabricating such dual-orientation substrates, which are also called hybrid orientation substrates. Methods known from this document are based on direct-silicon-bonded (DSB) substrates, which have a (110)-oriented silicon surface layer bonded to a (100)-oriented silicon wafer. The fabrication of well-defined lateral regions with different crystal orientations is in some known methods performed by fabricating shallow trench isolations (STI) in a masked etching and filling process, followed by chemical mechanical polishing. Subsequently, a resist layer is deposited and patterned to protect those lateral regions from a subsequent amorphization step, which are to retain their (110)-orientation in the finished substrate. The amorphization is then performed by implanting suitable ions such as silicon or germanium. Subsequently, a so lid-phase-epitaxial regrowth is performed, using the (100)-oriented substrate as the template for recrystallization of the amorphized lateral surface layer regions. With removal of the resist layer, the fabrication of a dual-orientation substrate is completed.
However, as is described in US 2006/0276011 A1, defects are created in this process, which are detrimental for device performance. Specifically, crystallographic defects are generated at the STI edge during the solid-phase epitaxy step. STI-edge defects are a major source of junction leakages in a transistors with a wide active area since those defects are placed in junction depletion region. In case of a narrow active area, i.e., reduced STI-to-STI spacing, STI-edge defects are also a mobility degradation factor since the defects are placed in the transistor channel below the gate. Since those defects are a major source of junction leakages, some solutions have been proposed in US 2006/0276011 to reduce the defect density. In particular, a high-temperature annealing step for defect reduction and an integration scheme that uses the solid-phase epitaxy before the STI formation are proposed. The latter concept is explained in the following with reference to FIGS. 1 to 4.
FIGS. 1 to 4 show schematic cross-sectional views of a dual-orientation silicon substrate during different stages of its fabrication.
Initially, a DSB silicon substrate 100 is provided. The DSB substrate has a (100)-oriented silicon substrate 102 and a (110)-oriented silicon surface layer 104 on top of the substrate 102. Note that, in the context of the present invention, numbers in round brackets indicate crystal orientations while numbers which are not bracketed are used as reference labels.
In a subsequent processing step, the result of which is shown in FIG. 2, a resist layer 106 is deposited on the surface layer 104 and lithographically patterned to provide openings in first lateral regions of the resist layer 106, which correspond to first lateral regions 108 of the surface layer, in which a (100)-oriented surface is desired. Then, an amorphizing ion implant 110 indicated by arrows pointing towards the substrate 100 is performed. Due to the resist pattern 106 provided in previous processing, the amorphization is performed only in the first lateral region 108, the ion implant 110 thus leads to an amorphized silicon layer 112. The amorphized silicon layer 112 extends slightly deeper into the substrate than the surface layer 104. Therefore, the amorphized layer 112 is arranged on top of a (100)-oriented substrate region of the substrate 102. The amorphized layer 112 is then recrystallized by a recrystallization anneal in order to establish a (100)-orientation of the substrate 100 in the first lateral region 108. As shown in FIG. 3, the resist layer 106 has also been removed at this processing stage, revealing second lateral regions 114 of the surface layer 106 with (110)-orientation.
As is shown in FIG. 3, a lateral defect region 116 is generated in the course of the amorphization and recrystallization process. The lateral extension 1 of the lateral defect region 116 roughly corresponds to the thickness d of the originally deposited surface layer 104.
In subsequent processing, STI regions 118 are fabricated in the lateral defect regions 116. In further processing steps, end-of-range defects (not shown) at the former interface between amorphized layer 112 and the substrate 102 are removed by a high-temperature defect-removal anneal.
The processing of US 2006/0276011 A1 has the disadvantage of not being applicable in future CMOS technology nodes with advanced scaling. Moreover, it is not fully compatible with the integration of thin-film devices. Also, the processing scheme is vulnerable to short-channel effects.
FIGS. 5 and 6 show schematic cross-sectional views of different CMOS semiconductor devices 500 and 600. The figures are used to illustrate main causes of junction leakages in semiconductor devices integrated on DSB substrates. In both devices, an nMOSFET 502 and 602, respectively, and a pMOSFET 504 and 604, respectively, are shown. The devices are provided on a dual-orientation substrate 506 and 606, respectively. The two devices 500 and 600 differ in the depth extension d of the (110)-oriented surface layer 508 and 608, respectively. The (110)-oriented surface layer 508 has a depth extension d that reaches deeper than source and drain regions 512 and 514 of the pMOS transistor 504. In the case of the semiconductor device 600, the (110)-oriented surface layer 608 has a smaller depth extension than the source and drain regions 612 and 614 of the pMOS transistor 604. The larger depth extension of the surface layer 508 avoids junction leakages in the pMOS transistor 504 of the semiconductor device 500. However, defect regions 516 and 518 are present in the nMOS transistor 502. The defect regions 516 and 518 extend along sidewalls of STI regions 520 and 522, which define the (100)-oriented, recrystallized first lateral surface region of the dual-orientation substrate 506. These defect regions 516 and 518 form a source of leakages as they extend into source and drain regions 524 and 526 of the nMOS transistor 502.
Therefore, defect problems are present in CMOS semiconductor devices on dual-orientation substrates, with different leakage problems being present in semiconductor devices with surface layers of different thickness.
Thus, one of the main challenges is to provide a dual-orientation substrate which avoids leakage problems in semiconductor devices such as transistors and which can be fabricated also at advanced scaling of the width of the isolation regions and the spacing between isolation regions on opposite lateral sides of an active area.